Inside the Chip Supply Chain: EUV, Fabs and HBM

Every leading-edge chip on the planet is printed by machines from one Dutch company, and there is no second supplier. That single fact shapes more of the semiconductor industry’s economics than any technology roadmap does, and in 2026 it sits alongside a newer constraint: the industry can now fabricate more logic dies than it can package and pair with high-bandwidth memory. Here is how the chokepoints actually work, with the numbers taken from filings and official announcements rather than from conference slides.

One company, one machine, no substitute

Extreme ultraviolet lithography prints features using 13.5 nm light generated by firing a high-power laser at droplets of molten tin roughly 50,000 times a second. The optics cannot use lenses at that wavelength because everything absorbs it, so the system relies on multilayer mirrors of near-atomic precision supplied by Carl Zeiss SMT, and the light source traces back to Cymer, which ASML acquired. Nobody else ships a production EUV scanner. Canon and Nikon compete in deep-ultraviolet immersion tools; neither has an EUV product.

The scale of the dependency is easy to underestimate. In its 2025 annual report ASML recognised revenue on 48 EUV systems for the year, against 44 in 2024, on total net sales of €32.7 billion. On its Q2 2026 results the company reported €9.3 billion of net sales and said it plans to add 30% to its 2026 low-NA EUV capacity of around 65 systems for 2027, and is investigating another 30% increase for 2028. Full-year 2026 guidance was raised to €43–45 billion.

Read that capacity figure again. The entire world’s supply of leading-edge logic and advanced DRAM is gated by a production line that builds on the order of 65 machines a year. TSMC’s own capital budget for 2026 is $60–64 billion, roughly the same order of magnitude as ASML’s total annual revenue, which tells you how much of a fab’s cost is a small number of extremely expensive tools.

The next generation, High NA EUV, raises the numerical aperture from 0.33 to 0.55 and shrinks the printable feature further, at the cost of a halved exposure field that forces designers to stitch large dies. These tools have been widely reported at roughly $380–400 million each, several times the price of a standard EUV scanner. On 15 July 2026, Intel and ASML said Intel Foundry had become the first to run High NA EUV in high-volume production, on Panther Lake client processors. TSMC has been publicly cooler on High NA, arguing that multi-patterning with existing 0.33 NA tools remains cheaper for now.

What a “node” name actually measures

Nothing physical. “3 nm” is not a dimension you can find on the die. Since roughly the 22 nm generation, node labels have been marketing designations, and the three leading foundries do not use the same yardstick. The figures that matter to a designer are contacted gate pitch, metal pitch, standard-cell height and the resulting transistor density, plus the switching-energy and drive-current curves.

The practical consequence: Intel’s “18A” and TSMC’s “N2” are not comparable because their names say so, and a chip company evaluating both has to compare PPA data under NDA. What node names do reliably signal is generational ordering within one vendor, and revenue mix. TSMC’s Q2 2026 earnings release shows how concentrated that mix has become.

The same release put quarterly revenue at NT$1,270.38 billion (US$40.20 billion) with a 67.7% gross margin, and guided Q3 2026 revenue to US$44.6–45.8 billion. A 67% gross margin in a capital-intensive manufacturing business is the price of being the only credible supplier at the top nodes.

What a fab actually costs

Public numbers for a single leading-edge fab shell plus tools now sit in the tens of billions. TSMC’s 4 March 2025 announcement committed US$165 billion in the United States for three fabs, two advanced packaging facilities and an R&D centre. In July 2026, alongside its Q2 results, the company added a further $100 billion and at least four more Arizona facilities, taking the reported site total to around $265 billion.

A rough worked example of why the arithmetic is brutal. Assume a leading-edge fab needs on the order of 15 EUV scanners to reach volume. At even a conservative $200 million per low-NA system, that is $3 billion of lithography alone, before deposition, etch, metrology, the cleanroom, or the multi-year ramp during which yields are too low to sell most of what you make. Depreciation on that base has to be recovered inside roughly five years, which is why foundry pricing at N2 and below is set by scarcity rather than by cost-plus.

Packaging and HBM: where the queue actually is

Through 2025 and into 2026 the binding constraint on AI accelerators has not been front-end wafer capacity. It has been advanced packaging, principally TSMC’s CoWoS family, and the supply of high-bandwidth memory that goes into those packages. An accelerator is a logic die (or several) plus a stack of HBM on an interposer; if either the interposer capacity or the memory stacks are short, the logic wafers sit in inventory.

SK hynix said on 12 September 2025 that it had completed development of HBM4 and established a mass-production system, quoting a 2,048-terminal interface, operating speed above 10 Gbps against the JEDEC standard of 8 Gbps, and more than 40% better power efficiency, built on its 1bnm DRAM process. That doubling of the interface width is the reason HBM4 needs a logic base die from a foundry rather than a pure memory process, which pulls the memory makers into the same packaging queue as everyone else.

HBM is priced and allocated more like a capital good than a commodity: 2026 supply was reported as effectively committed to buyers before the year began, which removes the usual DRAM price cycle from the AI part of the market.

Export controls: what changed, and what it changed

US controls on advanced computing chips have gone through several revisions. A Bureau of Industry and Security rule dated 15 January 2025 pushed due-diligence obligations onto foundries and packaging houses, requiring transistor-count verification or attestation from approved designers, and added 16 entities to the Entity List including Sophgo.

The bigger shift came a year later. A BIS final rule effective 15 January 2026 replaced the presumption of denial for certain high-performance AI chips going to China and Macau with case-by-case review, for parts below a total processing performance of 21,000 and total DRAM bandwidth of 6,500 GB/s. Per Morgan Lewis’s analysis, BIS named Nvidia’s H200 and AMD’s MI325X as examples, and attached conditions including that shipments to China and Macau not exceed 50% of an exporter’s US sales, that US supply not be diverted, and that shipments be tested by independent US laboratories. Re-exports from third countries remain denied. A separate White House announcement on 14 January 2026 set 25% tariffs on semiconductors at matching performance thresholds.

Two second-order effects are worth planning around. First, controls on equipment have been more consequential than controls on chips, because a fab denied EUV cannot substitute; Chinese producers have pushed DUV multi-patterning further than most Western analysts expected, at a yield and cost penalty. Second, every tightening has accelerated domestic substitution programmes it was meant to slow.

Subsidy programmes and what they actually bought

The US CHIPS Act appropriated $39 billion for commercial fab incentives within a $50 billion CHIPS for America Fund. Congressional Research Service tracking records 19 companies with final awards totalling $30.7 billion plus $5.5 billion in loans across 40 commercial fab projects, with TSMC Arizona at $11.565 billion, Intel at $7.865 billion, Micron at $6.165 billion and Samsung at $4.745 billion. In August 2025 the arrangement with Intel was restructured so that $8.9 billion of federal funding converted into a 9.9% equity stake, making the US government Intel’s largest single shareholder.

Elsewhere the picture is thinner. The European Commission presented a Chips Act 2.0 proposal on 3 June 2026 with faster permitting and demand-side measures, conceding that Europe still accounts for under 10% of global production despite the first Act mobilising more than €52 billion; the proposal is at the start of the legislative process, not in force. Japan’s Rapidus announced on 27 February 2026 a ¥267.6 billion round, ¥100 billion of it government money via IPA and ¥167.6 billion from 32 private companies, targeting 2 nm mass production in 2027.

Four things to check before you plan around silicon supply

1. Ask about packaging, not wafers. If your product needs an accelerator, your lead time is set by CoWoS-class capacity and HBM allocation, not by whether N2 wafers exist.
2. Treat node names as vendor-internal. Get contacted gate pitch, cell height and power-performance curves under NDA before comparing foundries.
3. Model equipment lead times, not just fab announcements. A fab announcement is a claim on ASML’s roughly 65-unit annual low-NA EUV output; groundbreaking dates say little about when wafers ship.
4. Re-read your export-control exposure each quarter. The 2026 thresholds are numeric and specific, which makes them straightforward to check and easy to breach if a product is re-spun.

As of 2026 the honest summary is that the industry has money and has political attention, and still has exactly one supplier for the machine at the centre of it.

Sources

• ASML — 2025 Annual Report, financial performance section
• ASML — Q2 2026 financial results
• TSMC — Second Quarter 2026 earnings release
• TSMC — Intends to Expand Its Investment in the United States to US$165 Billion
• SK hynix Newsroom — Completes World’s First HBM4 Development and Readies Mass Production
• Congressional Research Service — Semiconductor Fabrication Facilities Funded by the CHIPS Act
• US Bureau of Industry and Security — Commerce Strengthens Restrictions on Advanced Computing Semiconductors
• Rapidus — Secures 267.6 Billion Yen in Funding